1. Field of the Invention
This invention relates generally to computer hardware and, more particularly, to a device combining a processor, a dynamic random access memory (DRAM) and an input/output (I/O) bus in a system-on-a-chip.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors, as well as a continual reduction in the lengths of the interconnections connecting the semiconductor devices that comprise the integrated circuit devices. Thus, there is a constant drive to reduce the size, or scale, of the components and/or the interconnection lengths of atypical integrated circuit device to increase the overall speed of the integrated circuit device, as well as devices incorporating such integrated circuit devices.
However, the incorporation of many different components, such as a processor and an input/output (I/O) bus and the like onto a single chip, to provide a reduction in the interconnection lengths connecting these various components, has been frustrated by the inability to provide adequate memory storage capacity onto the same chip. For example, conventional integrated circuit devices typically provide a dynamic random access memory (DRAM) chip separate and apart from the chip having the processor thereon. This leads to an increase in the interconnection lengths connecting the processor and the dynamic random access memory (DRAM) and decreases the overall speed of the conventional integrated circuit device.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.